The present invention relates to information storage devices, and more specifically to sense amplifiers for a resistive bit used as part of a memory device.
New materials are now making it possible to produce multibit memory cells that are able to have more then just two states. Materials having a perovskite structure, among them colossal magnetoresistance (CMR) materials and high temperature superconductivity (HTSC) materials are materials that have electrical resistance characteristics that can be changed by external influences.
For instance, the properties of materials having perovskite structures, especially for CMR and HTSC materials, can be modified by applying one or more short electrical pulses to a thin film or bulk material. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material. The pulse is of low enough energy so as not to destroy, or significantly damage, the material. Multiple pulses may be applied to the material to produce incremental changes in properties of the material. One of the properties that can be changed is the resistance of the material. The change may be at least partially reversible using pulses of opposite polarity from those used to induce the initial change.
The resistance of the material forming the resistive bit can vary over a range of values. Allowing a single resistive bit to support more than one equivalent binary bit worth of data. It may be possible for single resistive bit to store a value that is equivalent to several binary its.
A read circuit is provided to convert a value stored in a resistive bit into an equivalent binary output. The read circuit comprises a voltage input from the resistive bit connected to a first bit-sensing and a second bit-sensing amplifier. The first bit-sensing amplifier comprises a input node connected to the voltage input, a first output bitline and a first source. The second bit-sensing amplifier comprises an input node connected to the voltage input, a second output bitline and a second source. The first output bitline is connected to an inverter that has an output connected to a voltage divider. The voltage divider comprises FETs in series between the inverter output and a level adjustment input, which corresponds to a FET source, which is connected to the first source. The voltage divider further comprises a divider output connected to the second source. The connection from the voltage divider to the second source provides an offset allowing the second bit-sensing amplifier to reset its binary output when the input voltage is higher than an initial switching voltage of the second bit-sensing amplifier.